1. Design and analysis of VRCA64

  1. Source edi.sh and synopsys.sh to run EDI and PrimeTime.

  2. Go to directory 3-as in the top-level directory.

  3. Go to directory VRCA64. The files in this directory are the same as those used in the tutorial.

  4. We used 0.6 (60%) for the initial utilization in the tutorial. Redesign the layout using 0.4 for the initial utilization.

  5. What to submit

    1. Timing reports (obtained by running "report_timing") after placement, CTS, routing, and postRoute optimization.

    2. A final timing report obtained by PrimeTime.

      • Do not show the whole reports. Copy and paste (or screen-capture) only summary parts as follows:


2. Design and analysis of VCLA256

  1. This design is a 256-bit carry-lookahead adder.

  2. Go to directory 3-as/VCLA256.

  3. Design a layout of VCLA256. Use the following settings.

  4. What to submit

    1. Timing reports (obtained by running "report_timing") after placement, pre-CTS optimization, routing, and postRoute optimization.

    2. A screen-shot of the final layout (after post-route optimization).

    3. A final timing report obtained by PrimeTime.


3. Wirelength vs. utilization

  1. Redesign VCLA256 using five different utilization values (0.5, 0.55, 0.6, 0.65, and 0.7). (you design five different layouts)

  2. You can find the final wirelength in the log.

  3. Plot a graph whose x-axis and y-axis are the utilization and the final wirelength, respectively.

  4. Do you see any trend in the graph?

  5. What to submit

    1. The utilization-wirelength plot.

    2. Discussion on the relationship between the final wirelength and the utilizaiton.