Research


 

 

     

(1) Current Research Interests: My current research principally revolves around the broad topic Network on Chip (NoC), which has emerged as the communication backbone for multi-core chips. With my graduate students and collaborators I am working on the following projects.

  • On-chip wireless communication network: Recent investigations have established that the silicon integrated on-chip antenna operating in the millimeter wave range of a few tens to one hundred GHz is now a viable technology. Moreover excellent emission and absorption characteristics leading to antenna like behavior in carbon nanotubes (CNTs) are observed recently. In this project we are working on the design methods for wireless NoCs with different types of on-chip antennas. Our aim is to design wireless NoC architectures based on small-world graphs. Small-world graphs have a very short average path length, defined as the number of hops between any pair of nodes. The average shortest path length of small-world graphs is bounded by a polynomial in log(N), where N is the number of nodes, making them particularly interesting for efficient communication with minimal resources. NoCs incorporating small-world connectivity can perform significantly better than locally interconnected mesh-like networks, yet they require far fewer resources than a fully connected system.
  • NoC-based hardware accelerators for Biocomputing: The gap between data generation and data processing is rapidly widening in biocomputing applications, and to close this gap it is imperative to assimilate the latest of breakthroughs in the Integrated Circuit (IC) design community into mainstream biocomputing research. Integrating huge number of processing cores on a single chip can help realize orders of magnitude improvement in performance and eventually will bridge the gap between data generation and data processing. In this project our aim is to design NoC-based hardware accelerators for different biocomputing applications, like sequence alignment and phylogenetic tree construction.
  • Sustainable Computing: While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This project aims to investigate new, far-reaching design methodologies that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.
  • Machine Learning inspired Three-dimensional (3D) NoC Architectures: Three-dimensional (3D) Network-on-Chip (NoC) is an emerging technology that has the potential to achieve high performance with low power consumption for multicore chips. However, to fully realize their potential, we need to consider novel 3D NoC architectures. In this work, inspired by the inherent advantages of small-world (SW) 2D NoCs, we explore the design space of SW network-based 3D NoC architectures. We leverage machine learning to intelligently explore the design space to optimize the placement of both planar and vertical communication links for energy efficiency.
    (2) Graduate Student Supervision:

    (a) Current Graduate Students:     
    1.      Ryan Kim (PhD), Co-advising with Radu Marculescu, CMU
    2.      Teng Lu (PhD), Co-advising with Behrooz Shirazi
    3.      Shervin Hajiamini (PhD), Co-advising with Behrooz Shirazi
    4.      Xian Li (PhD)
    5.      Dongjin Lee (PhD)
    6.      Wonje Choi (PhD)
    7.   Karthi Duraisamy (PhD)
    8. Sourav Das (PhD)
    9. Sheng-En (David) Lin (PhD), Co-advising with Dae Hyun Kim

    (b)
    Graduated:
    1. Jacob Murray (PhD, May 2014, currently Climical Asst. Professor, WSU, Everett)
    2. Paul Wettin (PhD, May 2014, currently with Marvel)
    3.  Turbo Majumder (PhD, May 2013, currently with Intel Labs)
    4.  Sujay Deb (PhD, May 2012, currently Asst. Professor, Indraprastha Institute of Information Technology (IIIT), Delhi, India)
    5.   Kevin Chang (PhD, May 2012, currently with ARM, Austin)
    6.  Amlan Ganguly (PhD, August 2010, currently Asst. Professor, Rochester Institute of Technology)
    7. Souradip Sarkar (PhD, December 2010, currently with Bell Labs)
    8. Haibo Zhu (MS, July 2007, currently employed at LINK_A_Media Devices, San Jose, USA)
    9. Brett Feero (MS, May 2008, currently employed at Apple)
    9. Divya Krishnan (MS, August 2010, currently working at Micron, Boise)
    10. Chien Chuan Hung (MS, currently working at Nvidia)

    (3) Research Grants (Total ~4.5 million):

    Serial No.

    Title

    Source

    Role

    Amount

    Duration

    (1)

    CAREER: Reliable On-Chip Wireless Communication Network for Multi-Core Systems

    NSF

    PI

    $450k

    07/01/09 - 06/30/14

    (2)

    DC: Small: Efficient Algorithms for Data-intensive Biocomputing

    NSF

    Co-PI

    $435k+$16k REU

    06/01/09 - 07/31/13

    (3)

    II-NEW: Acquisition of Test and Measurement Equipment Enabling Design of Wireless Networks-on-Chip for Multi-Core Systems

    NSF

    PI

    $645k

    02/01/11-02/01/14

    (4)

    SHF: CSR: Medium: Collaborative Research: Hierarchical On-Chip Millimeter-Wave Wireless Micro-Networks for Multi-Core Systems

    NSF

    Lead PI

    $800K

    06/01/12-05/31/16

    (5)

    Millimeter-Wave Wireless Network-on-Chip Architectures for Multi-Core Systems

    Army Research Office (ARO)

    PI

    $373K

    08/16/12-07/15/15

    (6)

    Collaborative Research: On-chip Multi-channel Millimeter-wave Wireless Links for Multi-core Platforms

    NSF

    Co-PI

    $490k

    10/16/12-10/15/15

    (7)

    Equipment for research on wireless network on chip architectures for multicore systems

    DURIP, ARO

    PI

    $250K

    8/1/13-7/31/14

      

    (8)
    REU Site: New-generation Power-efficient Computer Systems Design NSF
    Co-PI
    $323,660 05/01/14-04/30/17
    (9)
    SHF: NeTS: Medium: Collaborative Research: The Power of Less Wiring: Wireless NoC-enabled Voltage-Frequency Islands (VFIs) for Energy-Efficient Multicore Platforms NSF
    WSU PI
    $625,000 08/01/15-07/31/18
    (10)
    Student Travel Sponsorship for the IEEE/ACM International Symposium on Networks-on-Chip 2015 NSF
    PI
    $10,000
    07/15/15-07/14/16


       


     
       
     
           

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    Partha Pande, 2015