1. Synthesis

1. In the top-level directory, run the following command.

• source synopsys.sh

2. Go to the synthesis directory.

• cd 1-syn

3. In the directory, you will see the following files.

• VRCA64.v : Verilog RTL source code for a 64-bit ripple carry adder.

• VRCA64.tcl : A TCL script for synthesis.

4. Open the above files in a text editor and see how they look like.

5. Run Design Compiler.

• design_vision -no_gui

6. In Design Compiler, source the TCL script to load the library, the design, and the design constraints.

• design_vision> source VRCA64.tcl

7. Check the log messages. Make sure there is no ERROR.

8. Compile it. Make sure there is no ERROR.

• design_vision> compile -exact_map

9. Ungroup the design.

• design_vision> ungroup -all

10. Save the synthesized netlist. Note that "_m" in the output file name denotes for "mapped".

• design_vision> write -format verilog -output VRCA64_m.v

11. Save the design constraints.

• design_vision> write_sdc VRCA64_m.sdc

12. Close Design Complier.

• design_vision> exit

2. Check the output.

1. Open the mapped verilog netlist (VRCA64_m.v) in a text editor.

2. Check the followings.

• There is only one module named "VRCA64". We ungrouped the netlist, so there is no module hierarchy in the netlist.

• There are "wires". Wires are internal nets.

• There are a lot of gates such as DFF_X2, AOI22_X1, and so on.

3. Open the synthesis TCL script (VRCA64.tcl) and the design constraint file (VRCA64_m.sdc) in a text editor.

4. Check the followings.

• "set_max_capacitance" appears in both of them.

• "set_max_fanout" appears in both of them.

• "set_load" appears in both of them. In the TCL script, we used a wildcard character (*) for simplification. In the sdc file, you will see flattened constraints.

• Check other constraints too.

5. This is all. Now you are done with netlist synthesis.

3. Check the design.

1. Open Design Compiler again.

2. Run the following script to load the synthesized netlist. Make sure there is no ERROR.

• design_vision> source VRCA64_m_load.tcl

3. Check area. In my run, I get 195 ports, 451 nets, and 321 cells. The area for logic cells is 323.4um^2, that for F/Fs is 328.0um^2, and the total area is 651.4um^2.

• design_vision> report_area

4. Check timing. In my run, the worst path delay is 0.11ns (110ps).

• design_vision> report_timing

5. Check power. In my run, cell internal power is 97.6uW, net switching power is 16.9uW, and the total dynamic power is 114.5uW. Cell leakage power is 15.1uW.

• design_vision> report_power

6. There are a bunch of report functions. Try some to see the details of the design.

• design_vision> report_net

• design_vision> report_cell

• design_vision> report_clock