1. Introduction

Today's integrated circuits (ICs) have tens of millions of transistors, so it is impossible to design ICs without computer-aided design (CAD) tools.

A way to design ICs in a short development time is to use high-level languages called hardware description languages (HDLs) such as VHDL and Verilog. HDL source codes are compiled and converted into netlists. This process is called synthesis. Netlists contain cells(gates) and nets. Nets are wires that connect cells. Cells come from standard cell libraries made by standard cell designers and include complex cells such as full adder, as well as simple cells such as NAND and NOR.

Physical design makes layouts from the netlists. In this step, we do floorplanning, placement and routing. Floorplanning places blocks, which are sets of cells, on silicon. Floorplanning is followed by placement, which places standard cells. After placement, nets are routed automatically by routers. Power planning(routing of power/ground nets) and clock network synthesis(routing of clock nets) are also done before/after/during routing.

The final result is converted into gdsii format for fabrication. This file is tested for design rule checking (DRC), layout versus schematic (LVS), SPICE simulation, and so on.

2. Goal

In this assignment, you will design a few layouts using some CAD tools. The goal of this assignment is to experience a few CAD tools. You will also see how layouts are generated from netlists, what kind of files(information) are needed for placement and routing, etc.

3. Tools

The following tools will be used for this assignment:

Design Compiler (Synopsys): synthesis

Encounter Digital Implementation (EDI) System (Cadence): physical design

Virtuoso (Cadence): custom design

PrimeTime (Synopsys): timing and power analysis

Nangate 45nm library: standard cell library