* The first line is always a comment line. * Case-insensitive * Control .option post INGOLD=2 * Include the following file to load transistor models. .include './45nm_PTM_HP_v2.1.pm' * Parameters * Supply voltage .param Vsup = 1.0V * use NMOS_HP and PMOS_HP for NMOS and PMOS transistors. *** Transistor names should begin with "m". *** Use "nXXXXX" for node names. *** Use 0 for the ground. * Format: L(Length) W(Width) * Your netlist here *** Output load capacitance. Capacitors should begin with "c". * Format: cQ nQ 0 10f * Power supply * Format: *** Voltage source names should begin with "v". VVdd nVdd 0 Vsup * Input signal (independent voltage source) * Format: * For the signal, we use a piecewise linear (PWL) source. Format: ... PWL time1 value1 time2 value2 ... VCK nClk 0 PWL 0p 0 1n 0 1.01n Vsup 2n Vsup 2.01n 0 3n 0 3.01n Vsup 4n Vsup 4.01n 0 5n 0 5.01n Vsup 6n Vsup 6.01n 0 7n 0 7.01n Vsup 8n Vsup VD nD 0 PWL 0p 0 1.5n 0 1.51n Vsup 3.5n Vsup 3.51n 0 5.5n 0 5.51n Vsup 7.5n Vsup 7.51n 0 .measure TRAN rdly TRIG V(nClk) VAL=0.9 RISE=2 TARG V(nQ) VAL=0.9 RISE=1 .measure TRAN fdly TRIG V(nClk) VAL=0.9 RISE=3 TARG V(nQ) VAL=0.1 FALL=2 .measure TRAN ivdd AVG I(VVdd) FROM=3n TO=7n * Transient analysis. Simulate up to 2.5ns. .tran 1p 8n .end