0. Specification

• Input: clock, reset_n, in_data_src1[7:0], in_data_src2[7:0], in_data_src3[7:0]
• Output: out_data[2:0], out_state[1:0]

1. Function

• Clock (clock): positive-edge-trigered, 1MHz
• Reset (reset_n): active-low (reset the system when reset_n=0)
• When reset, deassert all the output signals (set them to zero)