Exercises for Appendix B

Put all of your answers in a single file and submit using the class turnin page.

Due: 5PM on Friday, Oct. 17.

These problems are on the CD that accompanies your textbook. You will need to refer to Appendix B, also on the CD. We will not be covering any material related to the Verilog language.

  1. Read Problem B.1 then do problem B.2 (in the "In more depth section").
  2. Problems B.3, B.4, B.5 and B.6 (in the "For more practice" section). In B.5 and B.6 the wording is misleading. You will need more than one gate to implement AND and OR using NOR or NAND. Info you need to do B.5 and B.6 is found in B.1 and B.2.
  3. Problem B.15 (in the "In more depth section").
  4. Problems B.7, B.11, and B.13 (in Appendix B proper)
  5. Problem B.37 (in "For more practice"); just show the states and the transitions -- you don't have to worry about the clock that causes the transitions, just assume that they happen spontaneously.