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Intel x86 Processors
CptS 260 - Intro to Computer Architecture Washington State University |
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The Intel x86 instruction setSpecial/general purpose registerseax, ebx, ecx, edx - 32 bit ax is low-order 16 bits of eax ah and al are the upper and lower 8 bits of ax esi and edi - source and destination index registers, si and di are the lower 16 bits esi and edi have special roles in memory-to-memory move operations esp - the stack pointer, sp is the low-order 16 bits ebp - the base pointer, same role as fp in the MIPS CPU eip - the instruction pointer (manipulated by branch/jump instructions) eflags- the flags register (not manipulated as a whole, but individual bits have names: CF - carry flag, PF - parity flag, ZF - zero flag, SF - sign flag, DF - direction flag, OF - overflow flag; CF, OF, PF, SF, ZF are set automatically by instructions affecting EAX. Operands The x86 supports a wide variety of values as direct operands of instructions: register, immediate, memory direct, or register indirect. Operands may be 8, 16, or 32 bits; confusingly in some assemblers these are termed byte, word, and doublewords while in others they are byte, word, and long operands. AssemblersThere are at least two families of assemblers for the x86, Intel-style and AT&T style, and they have radically different syntax. See the 80386 section of the GNU assembler manual. The Jones forth system is written in gnu assembler which uses the AT&T style. Some things to watch for
Instruction stylesMany Intel instructions have %eax as an implicit destination register, e.g. push and pop. Other instructions have other registers as implicit sources or destinations. We'll try to get a sense of this reading the jonesforth code. |
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