Objectives: To provide a sound background on computer architecture. The main focus of this course is processor design and evaluation with case studies. A number of architectural alternatives are described and evaluated using quantitative approaches

Homework Assignments

Homework 1: Assignment. Code_shell. Example  (Due: January 31, 9:10AM)

Homework 2: Assignment.  (Due: Feb. 7, 9:10AM)

Homework 3: Assignment.  (Due: Feb. 9, 9:10AM)

Homework 4: Assignment.  (Due: Feb. 16, 9:10AM)

Homework 5: Assignment.  (Due: Feb. 25, 9:10AM)

Homework 6: Assignment.  (Due: March 9, 9:10AM)

Homework 7: Assignment.  (Due: March 28, 9:10AM)

Homework 8: Assignment.  (Due: April 22, 9:10AM)  Solution

 

 

Lecture (Wednesday, February 23. 12noon CUB 406)

"Nanoelectronics" by Jose Delgado-Frias, EECS, WSU

Lecture (Friday, April 8)

"Introduction to ARM Processors" by Brett Feero, Design Engineer, ARM, Inc.

 

Handouts

Chapter 1: Introduction

Chapter 2: Instruction Set Architecture

Chapter 3: Arithmetic and Floating Point

                 - Adder and Multiplier

Chapter 4: Processor Datapath & Control

                   Pipelining

                   Datapath forwarding

                   Branch prediction

                   Inst. Level Parallelism (ILP)

Chapter 5: Cache Memory

 

 

Project

▪ Description

▪ Trace example

▪ Link to traces (4-6MB files)

▪ Deadlines:

   - Team members due: March 23, 2011 (send email by 12noon)

   - Mid-project report due: April 18, 2011 at 9:10am

       Mid-project report spec's / sample trace for mid-project report: sampletrace_500

   - Final project report with all the results is due: April 29 at 9:10am. May 3, 5pm

       Project report: description and traces (4-6MB files)

 

Exams

Exam 1:  February 28, 2011  (Sample: 2010 Exam 1)

Exam 2: April 4, 2011 (Chapter 4: from pipelining to ILP)

Final Exam:  Tuesday, May 3, 2011 (9AM) Solution to Homework 8

 

Contact: jdelgado@eecs.wsu.edu ( 509/335-1156 )
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