2004

L. Zhao and J. G. Delgado-Frias, “An Efficient Scheme Against Various Attacks in Ad Hoc Networks,” International Conference on Communication and Computer Networks (CCN 2004), Cambridge, Mass., November 8-10, 2004.

J. J. Rooney, J. G. Delgado-Frias and D. H. Summerville, “An Associative ternary cache for IP routing” IEE Proceedings Section E: Computers and Digital Techniques, vol. 151, no. 6, pp. 409-416, November 2004.

R. Guo and J. G. Delgado-Frias, “A Pipelined Cache Architecture for IPv6 Lookups,” International Conference on Communication and Computer Networks (CCN 2004), Cambridge, Mass., November 8-10, 2004.

R. He and J. G. Delgado-Frias, “Overflow buffer in crossbar -A new architecture for high performance routers,” International Conference on Communication and Computer Networks (CCN 2004), Cambridge, Mass., November 8-10, 2004.

M. Myjak, D. Blum, and J. Delgado-Frias, Enhanced fault-tolerant CMOS memory elements, in Proc. 2004 IEEE International Midwest Symposium on Circuits and Systems, Hiroshima, Japan, Jul. 2004.

L. Zhao and J. G. Delgado-Frias, “Protect Multiple Attacks in Ad Hoc Networks by Using Diversity Routing,” The 8th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida, July 18 - 21, 2004.

J. G. Delgado-Frias and R. Guo, “A Cache Architecture for IPv6 Lookups,” The 8th World Multiconference on Systemics, Cybernetics and Informatics, Orlando, Florida, July 18 - 21, 2004.

M. Myjak, F. Anderson, and J. Delgado-Frias, H-tree interconnection structure for reconfigurable DSP hardware, in Proc. 2004 International Conference on Engineering of Reconfigurable Systems and Algorithms, Las Vegas, NV, pp. 170-176, Jun. 2004.

M. Myjak and J. Delgado-Frias, Pipelined multipliers for reconfigurable hardware, in Proc. 2004 Reconfigurable Architectures Workshop, Santa Fé, NM, pp. 150-156, Apr. 2004.

2003

J. Nyathi and J. G. Delgado-Frias, "A Hybrid Wave-Pipelined Network Router," IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol.49, no. 12, pp.1764-1772, December 2003. (PDF)

M. J. Myjak and J. G. Delgado-Frias, A Two-Level Reconfigurable Architecture for Digital Signal Processing, The 2003 International Conference on VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.(PDF)

D. R. Blum and J. G. Delgado-Frias, A Fault-Tolerant Memory-Based Cell for a Reconfigurable DSP Processor, The 2003 International Conference on VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.

F. L. Anderson and J. G. Delgado-Frias, A Reconfigurable Crossbar Switch for a DSP Array, The 2003 International Conference on VLSI (VLSI'03), Las Vegas, Nevada, June 23-26, 2003.

J. G. Delgado-Frias, M. J. Myjak, F. L. Anderson, and D. R. Blum, A Medium-Grain Reconfigurable Cell Array for DSP Applications, IASTED International Conference on Circuits, Signal and Systems (CSS 2003), Cancun, Mexico, pp. 231-236, May 2003. (PDF)

S. Tatapudi, and J. G. Delgado-Frias, A VLSI Self-Compacting Buffer for Priority Queue Scheduling, IASTED International Conference on Circuits, Signal and Systems (CSS 2003), Cancun, Mexico, pp. 310-315, May 2003. (PDF)

J. G. Delgado-Frias and G. B. Ratanpal, "A VLSI Crossbar Switch with Wrapped Wave Front Arbitration,"  IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol. 50, no. 1, pp.135-141, January 2003. (PDF)

2001-2002

J. J. Rooney, J. G. Delgado-Frias and D. H. Summerville, An Associative Ternary Cache for IP Routing, Int. Conf. on Communications and Computer Networks (CCN 2002), Cambridge, Massachusetts, Nov. 4-6, 2002. (PDF)

J. G. Delgado-Frias and J. Nyathi, A Hybrid Wave-Pipelined Network Router, IEEE Annual Workshop on VLSI, Orlando, Florida, April 19-20, 2001.(PDF)

J. G. Delgado-Frias and G. Ratanpal, A VLSI Wrapped Wave Front Arbiter for Crossbar Switches, Great Lakes Symposium on VLSI, West Lafayette, Indiana, March 22-23, 2001. (PDF)

 V. Skormin, J. G. Delgado-Frias, D. McGee, J. Giordano, L. Popyack, V.Gorodetski, and A.Tarakanov, BASIS: Biological Approach to System Information Security,International Workshop on Mathematical Methods, Models and Architectures for Computer Networks Security, St. Petersburg, Russia, May 21-23, 2001.(PDF)