EDITED BOOKS
  • J. G. Delgado-Frias and W. R. Moore (Eds.), VLSI for Neural Networks and Artificial Intelligence, New York: Plenum 1994.
  • J. G. Delgado-Frias and W. R. Moore (Eds.), VLSI for Artificial Intelligence and Neural Networks, New York: Plenum 1991.
  • J. G. Delgado-Frias and W. R. Moore (Eds.), VLSI for Artificial Intelligence, Boston, MA: Kluwer Academic, 1989.


BOOK CHAPTERS 

  • W. Lin, J. G. Delgado-Frias, and D. C. Gause, “Traveling Salesperson Problems,” in Encyclopedia of Electrical and Electronics Engineering, John G. Webster (Ed.), New York: John Wiley & Sons, Inc., vol. 22, pp. 546-560, 1999.
  • J. G. Delgado-Frias, S. Vassiliadis, G. G. Pechanek, W. Lin, S. Barber, and H. Ding, “A VLSI Pipelined Neuroemulator,” in VLSI for Neural Networks and Artificial Intelligence, J. G. Delgado-Frias and W. R. Moore (Eds.), pp. 71-80, New York: Plenum, 1994.
  • T. F. Ryan, J. G. Delgado-Frias, S. Vassiliadis, G. G. Pechanek, and D. M. Green, “A Dataflow Approach for Neural Networks,” in VLSI for Neural Networks and Artificial Intelligence, J. Delgado-Frias and W. Moore (Eds.), pp. 151-158, New York: Plenum, 1994.
  • J. G. Delgado-Frias, S. Vassiliadis, J. Goshtasbi, and G. Triantafyllos, “Architectural Schemes for Semantic Networks,” in Artificial Intelligence Methods and Applications, N. G. Bourbakis (ed.), pp. 516-540, World Scientific, 1992.
  • J. G. Delgado-Frias, “Computer Architectures for Artificial Intelligence and Neural Networks,” in Computer Engineering Handbook, (Chapter 10) C. H. Chen (Ed.), New York: McGraw-Hill, 1992.
  • J. G. Delgado-Frias, A. Ahmed, and R. Payne, “A Dataflow Architecture for AI,” in VLSI for Artificial Intelligence and Neural Networks, J. G. Delgado-Frias and W. Moore (Eds.), pp. 23-32, New York: Plenum 1991.
  • J. G. Delgado-Frias and W. R. Moore, “A Communication Scheme for Defect Tolerant Arrays,” in Defect and Fault Tolerance in VLSI Systems, C. H. Stapper and I. Koren (Eds.), New York: Plenum, 1990.
  • J. G. Delgado-Frias and W. R. Moore, “A WSI Semantic Network Architecture,” in VLSI for Artificial Intelligence, J. G. Delgado-Frias and W. R. Moore (Eds.), pp. 144-155, Boston, MA: Kluwer Academic, 1989.
  • J. G. Delgado-Frias, W. R. Moore and J. A. Trotter, “High Harvest Approaches for 2-D Arrays,” in Yield Modelling and Defect-Tolerance in VLSI, W. Moore, W. Maly and A. Strojwas (Eds.), pp. 191-202, Bristol, UK: Adam Hilger, 1988. 
 

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Last modified: March 2001