MSEE, Washington State University, 2003.

Ph.D., Washington State University, 2006

High Performance Low Power Systems, VLSI Design, Computer Architecture.

S. B. Tatapudi and J. G. Delgado-Frias, “A Mesochronous Pipelining Scheme for High- Performance Digital Systems,” IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol. 53, no. 5, pp. 1078-1088, May 2006.

J. G. Delgado-Frias, J. Nyathi and S. Tatapudi, “Decoupled Dynamic Ternary Content Addressable Memories,” IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol. 52, no. 10, pp. 2139-2147, October 2005.

S. B. Tatapudi and J. G. Delgado-Frias, “A Reduced Clock Delay Approach for High Performance Mesochronous Pipeline,” 49th IEEE Int. Midwest Symposium on Circuits and Systems, August 6-9, 2006.

S. B. Tatapudi and J. G. Delgado-Frias, “A Mesochronous Pipeline Scheme for High Performance Low Power Digital Systems,” 2006 IEEE International Symposium on Circuits and Systems, pp. 763-766, Kos, Greece, May 21-24, 2006.

S. B. Tatapudi and J. G. Delgado-Frias,  “Designing Pipelined Systems with a Clock Period Approaching Pipeline Register Delays,” 48th IEEE Int. Midwest Symposium on Circuits and Systems, Aug. 2005.  

S. B. Tatapudi and J. G. Delgado-Frias, “A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme,” pp. 191-197, The 2005 International Conference on Computer Design, pp. Las Vegas, June 2005.  

S. B. Tatapudi and J. G. Delgado-Frias, “A High Performance Hybrid Wave Pipelined Multiplier,” IEEE Computer Society Annual Symp. on VLSI, pp. 282-283, May 11-12, 2005.

S. Tatapudi, and J. G. Delgado-Frias, "A VLSI Self-Compacting Buffer for Priority Queue Scheduling," IASTED International Conference on Circuits, Signal and Systems (CSS 2003), Cancun, Mexico, pp. 310-315, May 2003. (PDF)