| PATENTS
U.S. PATENTS
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G.
G. Pechanek, S. Vassiliadis, and J. G. Delgado-Frias, “Massively
parallel array processor,” US 6,405,185,
June 11, 2002.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Massively Parallel Multiple-Folded
Clustered Processor Mesh Array,” US 6,041,398, issued: March 21, 2000.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Parallel Diagonal-Fold Array
Processor,” US 5,784,632, issued: July 21, 1998.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Massively Parallel Diagonal-Fold
Tree Array Processor,” US 5,682,544, issued: October 28, 1997.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Parallel Group Partitioned
Diagonal-Fold Switching Tree Computing Apparatus,” US 5,640,586; issued:
June 17, 1997.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Processing Element for Parallel
Array Processor,” US 5,612,908, issued: March 18, 1997.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Learning Machine Synapse Processor
System Apparatus,” US 5,613,044, issued: March 18, 1997.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Parallel Array Processor Interconnections,”
US 5,577,262, issued: November 19, 1996.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Learning Machine Synapse Processor
System Apparatus,” US 5,517,596, issued: May 16, 1996.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Learning Machine Synapse Processor
Apparatus,” US 5,483,620, issued: January 9, 1996.
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G. G. Pechanek,
S. Vassiliadis and J. G. Delgado-Frias, “Pyramid Learning Architecture
Neurocomputer,” US 5,325,464, issued: June 28, 1994.
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G. G. Pechanek,
S. Vassiliadis and J. G. Delgado-Frias, “Scalable Flow Virtual Learning
Neurocomputer,” US 5,329,611, issued: July 12, 1994.
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S. Vassiliadis,
G. Pechanek, and J. G. Delgado-Frias, “SPIN: A Sequential Pipelined Neurocomputer,”
US 5,337,395, issued: August 9, 1994.
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G. G. Pechanek,
S. Vassiliadis and J. G. Delgado-Frias, “Virtual Neurocomputer Architectures
for Neural Networks,” US 5,243,688, issued: September 7, 1993.
EUROPEAN AND WORLD WIDE PATENTS
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Massively Parallel Group
Partitioned Diagonal-fold Switching Tree Computing Apparatus,” EP0569764-A2,
issued: November 18, 1993 and EP0569764-A3, issued: July 13, 1994.
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G.
G. Pechanek, S. Vassiliadis, and J. G. Delgado-Frias, “A Massively Parallel
Diagonal Fold Tree Array Processor,” EP0569763-A2, issued: November
18, 1993 and EP0569763-A3, issued: July 13, 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Massively Parallel Array Processor,”
EP0564847-A2, issued: October 13, 1993 and EP0564847-A3, issued: July 20,
1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Virtual Neurocomputer Architectures
for Neural Networks,” EP0486684, issued: May 27, 1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Flow Virtual Learning
Neurocomputer,” EP0486635-A1, issued: May 27, 1992 and EP0486635-A4, issued:
March 23, 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Pyramid Learning Architecture
Neurocomputer,” EP0484522-A1, issued: May 13, 1992 and EP0484522-A4, issued:
March 23, 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “SPIN: A Sequential Pipelined
Neurocomputer,” EP0484507-A1, issued: May 13, 1992 and EP0484507-A4, issued:
July 15, 1992.
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G.
G. Pechanek, S. Vassiliadis, and J. G. Delgado-Frias, “A Learning Machine
Synapse Processor System Apparatus,” EP0484506-A1, issued: May 13, 1992
and EP0484506-A4, issued: March 23, 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Virtual Neurocomputer Architectures
for Neural Networks,” WO9201257A1, issued: January 23, 1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Pyramid Learning Architecture
Neurocomputer,” WO9118351A1, issued: November 28, 1991.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “A Learning Machine Synapse Processor
System Apparatus,” WO9118350A1, issued: November 28, 1991.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Flow Virtual Learning
Neurocomputer,” WO9118349A1, issued: November 28, 1991.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “SPIN: A Sequential Pipelined
Neurocomputer,” WO9118347A1, issued: November 28, 1991.
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