JOURNAL
PAPERS
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J.J. Rooney, J. G.
Delgado-Frias and
D. H. Summerville, An
Associative ternary cache for IP routing, IEE Proceedings Section E:
Computers and Digital Techniques, vol. 151, no. 06, pp. 409-416, November
2004. (PDF)
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J.
G. Delgado-Frias and G. B. Ratanpal, A VLSI Crossbar Switch with Wrapped Wave
Front Arbitration, IEEE
Transactions on Circuits and Systems, I: Fundamental Theory and Applications,
vol. 50, no. 1, pp.135-141, January 2003. (PDF)
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J.
Nyathi and J. G. Delgado-Frias, A Hybrid Wave-Pipelined Network Router, IEEE Transactions on Circuits and Systems,
I: Fundamental Theory and Applications, vol.49,
no. 12, pp.1764-1772, December 2003. (PDF)
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S. Vassiliadis,
M. Zhang, and J. G. Delgado-Frias, Elementary Function Generators for
Neural Network Emulators, IEEE Transactions on Neural Networks,
vol. 11, no. 6, pp. 1438-1449, November 2000. (PDF)
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J. G. Delgado-Frias
and J. Nyathi, A High-Performance Encoder with Priority Lookahead,
IEEE
Transactions on Circuits and Systems, I: Fundamental Theory and Applications,
vol.
47, no. 9, pp. 1390-1393, September 2000.(PDF)
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V. C. Aikens,
II, J. G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, A Neuro-Emulator
with Embedded Capabilities for Generalized Learning, Journal of
Systems Architecture, vol. 45, no.11, pp.1119-1143, July 1999. (PDF)
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A. DeLuca,
J. G. Delgado-Frias, and J. Hernandez, A Survey on Routers for Parallel
Architectures, Int. Journal on Instrumentation and Development,
vol.
8, no. 1, pp. 3-11, 1999.
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J. G. Delgado-Frias,
J. Nyathi, and D. H. Summerville, A Programmable Dynamic Interconnection
Network Router with Hidden Refresh, IEEE Transactions on Circuits
and Systems I: Fundamental Theory and Applications, vol. 45, no.11,
pp.1182-1190, November 1998.(PDF)
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, Executing Tree Routing Algorithms
on a High-Performance Pattern Associative Router, Journal of Systems
Architecture, vol. 44, no. 11, pp. 849-865, August 1998. (PDF)
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C-Y. Lu,
J. G. Delgado-Frias, and W. Lin, A Clustering and Genetic Scheme for
Large TSP Optimization Problems, Cybernetics and Systems: An International
Journal, vol. 19, no. 2, pp. 137-157, March 1998.
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A. E. Harvin,
III and J. G. Delgado-Frias, A VLSI Highly Pipelined Computing/ Communicating
Tree Structure, Journal of Microelectronic Systems Integration,
vol.
4, no. 4, pp. 237-248, December 1996.
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M. Zhang,
S. Vassiliadis, and J. G. Delgado-Frias, Sigmoid Generator for Neural
Computing Using Piece Wise Approximations, IEEE Transactions on
Computers, vol. 45, no. 9, pp. 1045-1049, September 1996.
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G. Triantafyllos,
S. Vassiliadis and J. G. Delgado-Frias, Software Metrics and Microcode
Development: A Case Study, Journal of Software Maintenance: Research
and Practice,
vol. 8, pp. 199-224, 1996.
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, A Flexible Bit-Associative
Router for Interconnection Networks, IEEE Transactions on Parallel
and Distributed Systems, vol. 7, no. 5, pp. 477-485, May 1996. (PDF)
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W. Lin, J.
G. Delgado-Frias, D. C. Gause, and S. Vassiliadis, A Hierarchical Genetic
Algorithm for the TSP, Journal of Mathematical Modelling and Scientific
Computing,
vol. 6, April 1996.
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H. D. Johnson,
J. G. Delgado-Frias, S. Vassiliadis, and D. M. Green, A Flexible Modeling
Approach for Assessing Multiprocessor Computers, Int. Journal of
Modelling and Simulation,
1996.
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J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, Flexible Oblivious Router Architecture,IBM
Journal of Research and Development, vol. 39, no. 3, pp. 315-334, May
1995.
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W. Lin, J.
G. Delgado-Frias, D. C. Gause, and S. Vassiliadis, A Hybrid Newton-Raphson
Genetic Algorithm for the Traveling Salesman Problem, Cybernetics
and Systems: An International Journal, vol. 26, no. 4, pp. 387-412,
1995.
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W. Chu, S.
Vassiliadis, and J. G. Delgado-Frias, The Multi-Associative Target Buffer:
A Cost Effective BTB Mechanism, Microprocessing and Microprogramming
Journal,
vol. 41, no. 3, pp. 211-225, 1995.
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J. G. Delgado-Frias,
S. Vassiliadis, H. D. Johnson, D. H. Summerville, D. M. Green, and A. De
Luca,A Processing Unit for Parallel Computer Organizations,
Int.
Journal on Instrumentation and Development, vol. 3, no. 4, pp. 20-32,
1994.
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J. G. Delgado-Frias,
S. Vassiliadis, C-L. Chu, and A. De Luca, DT: A Binary Tree Parallel
Computer with Distributed I/Os, Int. Journal on Instrumentation
and Development, vol. 3, no. 4, pp. 33-42, 1994.
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M. Zhang,
J. G. Delgado-Frias, and S. Vassiliadis, Table Driven Newton Scheme
for High Precision Logarithm Generation, IEE Proceedings Section
E: Computers and Digital Techniques, vol. 141, no. 5, pp. 281-292,
September 1994.
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J. G. Delgado-Frias
and D. M. Green, A Finite Difference Wafer-Scale Machine with Time-Redundant
Fault Tolerance, Journal of Microelectronic Systems Integration,
vol.
2, no.1, pp. 3-12, March 1994.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Folded Axon/Dendrite Tree Neurons:
A New Model for the Neural Paradigm, Valgo, La revue de l'Association
des Connexionnistes, no. 94-1, pp. 45-55, June 1994.
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C. Chang,
S. Vassiliadis, and J. G. Delgado-Frias, An Investigation of Binary
CLA and Ripple CMOS Adder Designs, Microprocessing and Microprogramming
Journal, vol. 40, pp. 1-21, 1994.
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S.
Vassiliadis, G. Pechanek, and J. G. Delgado-Frias, SPIN: The Sequential
Pipelined Neuro-emulator, International Journal on Artificial Intelligence
Tools, vol. 2, no. 1, pp. 117-132, 1993.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Many-SNAP, IBM Technical
Disclosure Bulletin, vol. 34, No. 10A, pp. 100-106, March 1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Shared Output SNAP,
IBM
Technical Disclosure Bulletin, vol. 34, No. 10A, pp. 107-110, March
1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, Digital Neural Emulators Using
Tree Accumulation and Communication Structures, IEEE Transactions
on Neural Networks, vol. 3, no. 6, pp. 934-950, November, 1992.
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J. G. Delgado-Frias,
S. Vassiliadis, and J. Goshtasbi, Semantic Network Architectures: An
Evaluation, International Journal on Artificial Intelligence Tools,
vol.
1, no. 1, pp. 57-83, 1992 (invited paper).
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J. G. Delgado-Frias
and W. R. Moore, A Semantic Network Architecture for Knowledge Base
Processing, Int. Journal for Engineering Application of Artificial
Intelligence, vol. 3, pp. 4-10, March 1990.
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J. G. Delgado-Frias
and W. R. Moore, Parallel Computer Architectures for AI Semantic Network
Processing, Int. Journal on Knowledge Based Systems, vol. 1,
no. 5, pp. 259-265, December 1988.
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