IBM
TECHNICAL REPORTS
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J. Park,
B. W. O’Krafka, S. Vassiliadis, and J. G. Delgado-Frias, “Survey on Routers,”
IBM Technical Report TR01.C766, pp. 1-34, IBM, Endicott, New York, April
1994.
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J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, “I/O Port Architecture and Organization,”
IBM Technical Report TR01.C767, pp. 1-12, IBM, Endicott, New York, April
1994.
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J. Park,
B. W. O’Krafka, S. Vassiliadis, and J. G. Delgado-Frias, “Design and Evaluation
of a DAMQ Multiprocessor Network Switch with Self-Compacting Buffers” IBM
Technical Report TR01.C768, pp. 1-60, IBM, Endicott, New York, April 1994.
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V.
C. Aikens, II, J. G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek,
“An Evaluation of Direct Neuroemulators,” IBM Technical Report TR51.0831,
IBM, Austin, Texas, March 1994.
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H. D. Johnson,
J. G. Delgado-Frias, S. Vassiliadis, and D. M. Green, “Synthetic Workload
Performance Characterization Models,” IBM Technical Report TR51.0830, IBM,
Austin, Texas, March 1994.
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W. Lin, J.
G. Delgado-Frias, G. G. Pechanek, and S. Vassiliadis, “Energy Functions
for a Neural Network Model for Optimization Problems: Evaluation and Eigen
Value Analysis,” IBM Technical Report TR 51.0827, IBM, Austin, Texas, February
1994.
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J. G. Delgado-Frias,
G. G. Pechanek, and S. Vassiliadis, “SPIN Prototype: The VLSI Sequential
Pipelined Neuroemulator,” IBM Technical Report TR 51.0807, IBM, Austin,
Texas, November 1993.
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S. Vassiliadis,
M. Zhang and J. G. Delgado-Frias, “Elementary Function Generators for Neural
Network Emulators,” IBM Technical Report TR 51.0802 IBM, Austin, Texas,
November 1993.
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D. H. Summerville,
J. G. Delgado-Frias, and S. Vassiliadis, “A Pattern Associative Router
for Tree Topology Implicit Routing Algorithms,” IBM Technical Report TR
51.0804, IBM, Austin, Texas, November 1993.
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H. D. Johnson,
J. G. Delgado-Frias, S. Vassiliadis, and D. M. Green, “A Petri Net Technique
for Assessing Performance of Loosely Coupled Multiprocessor Architectures,”
IBM Technical Report TR 51.0805, IBM, Austin, Texas, November 1993.
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H. D. Johnson,
J. G. Delgado-Frias, and S. Vassiliadis, “A Review of Dataflow Computing
Concepts and Architectures,” IBM Technical Report TR 51.0806, IBM, Austin,
Texas, November 1993.
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J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, “Flexible Oblivious Router Architecture:
Instruction Set and Organization,” IBM Technical Report TR01.C751, IBM,
Endicott, New York, September 1993.
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J. Park,
S. Vassiliadis, and J. G. Delgado-Frias, “Flexible Oblivious Router Architecture,”
IBM Technical Report TR01.C749, IBM, Endicott, New York, September 1993.
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G. G. Pechanek,
J. G. Delgado-Frias, and S. Vassiliadis, “A Massively Parallel Diagonal-Fold
Mesh Array Processor,” IBM Internal Technical Report TR 29.1655, pp. 1-41,
IBM, Research Triangle Park, North Carolina, May 1993.
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G. Triantafyllos,
S. Vassiliadis, and J. G. Delgado-Frias, “Error Distribution in Microcode
Development,” IBM Technical Report TR01.C659, pp. 1-19, IBM, Endicott,
New York, December 1992.
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S. Vassiliadis,
T. J. Eckenrode, G. Triantafyllos, and J. G. Delgado-Frias, “Multilinear
Regression Error Prediction Models,” IBM Technical Report TR01.C658, pp.
1-42, IBM, Endicott, New York, December 1992.
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G. Triantafyllos,
S. Vassiliadis, and J. G. Delgado-Frias, “Error Prediction Models Using
Program Metrics,” IBM Technical Report TR01.C657, pp. 1-90, IBM, Endicott,
New York, December 1992.
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G.
Triantafyllos, S. Vassiliadis, and J. G. Delgado-Frias, “An Analysis of
the Microcode Metrics Relationships,” IBM Technical Report TR01.C648, pp.
1-117, IBM, Endicott, New York, September 1992.
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J. G. Delgado-Frias,
S. Vassiliadis, and G. G. Pechanek, “A Processing Unit for Flexible Multiprocessor
Machine Organizations,” IBM Technical Report TR01.C417, pp. 1-17, IBM,
Endicott, New York, September 1992.
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M. Zhang,
J. G. Delgado-Frias, S. Vassiliadis, and G. G. Pechanek, “Hardwired Sigmoid
generator” IBM Technical Report TR01.C492, pp.1-38, IBM, Endicott, New
York, September 1992.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “A Learning Machine Synapse Processor
Architecture With Back-Propagation, Boltzmann Machine, and Matrix Processing
Examples,” IBM Technical Report TR01.C198, pp. 1-38, IBM, Endicott, New
York, 1991.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Hybrid Control Flow/Data
Flow Virtual Learning Neurocomputer,” IBM Technical Report TR01.C193, pp.
1-41, IBM, Endicott, New York, 1991.
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G.
G. Pechanek, S. Vassiliadis, and J. G. Delgado-Frias, “Scalable Digital
Neurocomputers Based on Novel Group Partitioning Algorithms,” IBM Technical
Report TR01.C195, pp. 1-41, IBM, Endicott, New York, 1991.
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G. G. Pechanek,
S. Vassiliadis, and J. G. Delgado-Frias, “Virtual Neurocomputer Architectures
for Neural Networks,” IBM Technical Report TR01.C044, IBM, Endicott, New
York, September 1991.
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S. Vassiliadis,
G. G. Pechanek, and J. G. Delgado-Frias, “Sequential Pipelined Neuroemulators,”
IBM Technical Report TR01.C042, IBM, Endicott, New York, September 1991.
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