Patents |
|
| 7,456,768 |
Analog-to-Digital Converters based on an Interleaving Architecture and associated methods; G. S. La Rue, H. Guo |
| 6,081,430 | High-Speed Backplane; G. S. La Rue |
| 5,777,505 |
Low-Power Crosspoint Switch; G. S. La Rue |
| 5,757,799 |
High-Speed Packet Switch; G. S. La Rue |
| 5,594,631 |
Digital Pulse Width Modulator for Power Supply Control; M. Katoozi, G. S. La Rue |
| 5,144,230 |
Method and System for Testing Integrated Circuits by Cycle Stealing; M. Katoozi, G. S. La Rue |
| 5,027,007 |
FFL/QFL FET Logic Circuits; G. S. La Rue, T. J. Williams |
| 4,798,978 |
GAAS FET Logic having Increased Noise Margin; G. M. Lee, C. M. Lee, G. S. La Rue |
| 4,716,311 |
Direct Coupled FET Logic with Super Buffer Output Stage; W. H. Davenport, G. D. McCormack, G. S. La Rue |
| 4,628,406 |
Method of Packaging Integrated Circuit Chips, and Integrated Circuit Package; K. R. Smith, K. H. Johnston,, G. S. La Rue, R. A. Mueller, S. A. Tabor |