Z. Zhou and G. S. La Rue, “A 12-bit Non-linear DAC for Direct Digital Frequency Synthesis,” IEEE Trans. on Circuits and Systems I, Vol. 55, No. 9, pp. 2459-2468, October, 2008.

P.  Sun, P. Upadhyaya, D.-H. Jeong, D. Heo and G. S. La Rue, “A Novel SiGe PIN Diode SPST Switch for Broadband T/R Module,” IEEE Microwave and Wireless Components Letters, Vol. 17, pp. 352-354, May 2007.

R. Zhang and G. S. La Rue, “Fast Acquisition Clock and Data Recovery Circuit with Low Jitter,” IEEE Journal of  Solid State Circuits, Vol. 41, pp. 1016-1024, May 2006.

C. L. Champion and G. S. La Rue, "Accurate SPICE Models for CMOS Analog Radiation-Hardness-by-Design," IEEE Trans. on Nuclear Science Vol. 52, pp. 2542-2549, December 2005.

C.A. Gossett, B. W. Hughlock, M. Katoozi, G. S. La Rue, S. A. Wender, ” Single Event Phenomena in Atmospheric Neutron Environments,” IEEE Transactions on Nuclear Science, Vol. 40, No. 6,  pp.1845-1852, July, 1993.

B. W. Hughlock, G.S. La Rue, A.H. Johnston, ”Single-Event Upset in GaAs E/D MESFET Logic,” IEEE Transactions on Nuclear Science, Vol. 37, No. 6, pp.1894-1901, Dec. 1990.

1989

B. Cheney, P. Hamilton and G. S. La Rue, "Design and Test of a 2-Gbit/s GaAs 16/8-bit MUX/DEMUX Pair," IEEE Journal of  Solid State Circuits, Vol. 24, No. 2, p. 463, April, 1989

1981

G. S. La Rue, J. D. Phillips and W. M. Fairbank, "Observation of Fractional Charge of (1/3)e on Matter," Physical Review Letters, Vol. 46, p. 967. 1981.

1979

G. S. La Rue, W. M. Fairbank and J. D. Phillips, "Further Evidence for the Existence of Fractional Charge 1/3e on Matter," Physcal Review Letters, Vol. 42, p. 142. 1979.

1978

G. S. La Rue, Thesis: "Measurement of Residual Charge on Superconducting Niobium Spheres" (unpublished)

1977

G. S. La Rue, W. M. Fairbank and A. F. Hebard, "Evidence for the Existence of Fractional Charge on Matter," Physical Review Letters, Vol. 38, p. 1011, 1977.

1988

A. F. Hebard, G. S. La Rue, J. D. Phillips and C. R. Fisel," Search for Fractional Charge," in "Near Zero, New Frontiers of Physics," W. H. Freemand and Co., 1988

J. Nickoloff, I. Horowitz and G. S. La Rue, "Open-Source Layout Generator using Foundry Design Rules for Radiation Hard Design" 13th NASA Symposium on VLSI Design, Post Falls, ID, June, 2007.

M. J. Zahller and G. S. La Rue, "40 Gbps SiGe Pattern Generator IC with Variable Clock Skew and Output Levels," IEEE Workshop on Microelectronics and Electron Devices, pp. 9-10 April 2006.

Z. Zhou and G. S. La Rue, “A Radiation-Hard Non-linear DAC for DDFS," 12th NASA Symposium on VLSI Design, Coeur d'Alene, ID, October, 2005.

Z. Zhou, I. Horowitz and G. S. La Rue, “Design of a Radiation-Hard DDFS,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 88-91 April 2005.

I. Horowitz and G. S. La Rue, “Parallel Phase Accumulator Architecture for DDFS,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 63-66 April 2005.

H. Guo and G. S. La Rue, “A Low-Power 16-bit 500 KS/s ADC,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 84-87 April 2005.

D. J. Robinson and G. S. La Rue, "1 GSps 11-bit track-and-hold in SiGe BiCMOS," IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 67-70 April 2005.

C. L. Champion, G. S. La Rue, "Accurate Modeling of FETs with Arbitrary Gate Geometries for Radiation Hardening," 4th Annual Rad Hard by Design Workshop, Albuquerque, NM, August, 2004.

R. Zhang and G. S. La Rue, “A Clock and Data Recovery Circuit with Fast Acquisition and Low Jitter,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 48-51, April 2004.

Z. Zhou and G. S. La Rue, “Non-linear DAC Implementations in DDFS,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 124-127, April 2004.

.Guo, C. Champion, D. M. Rector and G. S. La Rue, “A Low-Power Low-Noise Sensor IC,” IEEE/EDS Workshop on Microelectronics and Electron Devices, pp. 60-63, April 2004.

R. Zhang and G. S. La Rue, “Clock and Data Recovery Circuits with Fast Acquisition and Low Jitter,” IEEE 15th Biennial University/Government/Industry Microelectronics Symposium, ,” pp. 82-85, June 2003.

Z. Zhou, D. Betowski, X. Li, G. S. La Rue, V. Beiu “High Performance Direct Digital Frequency Synthesizers,” IEEE 15th Biennial University/Government/Industry Microelectronics Symposium, pp. 368-369, June 2003.

1999

G. S. La Rue, "Challenges and Trades in Broadband LEO Network Design," NASA SERC Symposium on VLSI Design, October, 1999.

1996

G. S. La Rue and T. A. Dao, "Gigabit Communication Circuits: 16:1 Multiplexer, 1:16 Demultiplexer and 16 x 16 Crosspoint Switch," International Solid-State Circuits Conference, February, 1996.

1993

G. S. La Rue, "Complementary HFET Technology for Space Applications," NASA SERC Symposium on VLSI Design, November, 1993

1992

G. S. La Rue and D. E. Grider, "Complementary HFET 32-bit Serial Multiplier," IEEE GaAs IC Symposium, October,1992

1990

G. S. La Rue and T. J. Williams, "FET FET Logic, a High Performance, High Noise Margin E/D MESFET Logic Family," IEEE GaAs IC Symposium, October, 1990

1990

G. S. La Rue and P. Y. Chan, "GaAs VLSI for Aerospace Electronics," NASA SERC Symposium on VLSI Design, November, 1990.

1990

T. Williams, H. S. Fuji, J.P. Harrang, R.R. Daniels, H. T. Griem, D. L. West, S. Ray, and G. S. La Rue, "High Yield Optical Integration Compatible InP-Based Circuits," Proceedings of the 2nd International Conference on InP and Related Materials, p. 181, April, 1990.

1990

D. K. Smith, D. J. Schneider, R. Fu, E. Chan, G. La Rue, T. Williams, M. Tanielian, "A 1 Gbps Fiber Optic Transmitter/Receiver Pair for Military Avionics Network Applications," DOD Fiber Optic Conference, 1990

1986

D. C. Larson, G. S. La Rue and G. D. Mc Cormack, "A GaAs Counter Family Designed Using Standard Cells," IEEE Custom IC Conference, May, 1986.

1983

G. S. La Rue, "A GHz GaAs Digital to Analog Converter," IEEE GaAs IC Symposium, Oct.1983.  

1983

A. Rode, T. Flegal and G. La Rue, "GaAs LSI Gate Array Technology and Applications," IEEE GaAs IC Symposium, Oct. 1983.