(1) Current Research Interests: My current research principally revolves around the broad topic Network on Chip (NoC), which has emerged as the communication backbone for multi-core chips. With my graduate students and collaborators I am working on the following projects.

• On-chip wireless communication network: Recent investigations have established that the silicon integrated on-chip antenna operating in the millimeter wave range of a few tens to one hundred GHz is now a viable technology. Moreover excellent emission and absorption characteristics leading to antenna like behavior in carbon nanotubes (CNTs) are observed recently. In this project we are working on the design methods for wireless NoCs with different types of on-chip antennas. Our aim is to design wireless NoC architectures based on small-world graphs. Small-world graphs have a very short average path length, defined as the number of hops between any pair of nodes. The average shortest path length of small-world graphs is bounded by a polynomial in log(N), where N is the number of nodes, making them particularly interesting for efficient communication with minimal resources. NoCs incorporating small-world connectivity can perform significantly better than locally interconnected mesh-like networks, yet they require far fewer resources than a fully connected system.
• NoC-based hardware accelerators for Biocomputing: The gap between data generation and data processing is rapidly widening in biocomputing applications, and to close this gap it is imperative to assimilate the latest of breakthroughs in the Integrated Circuit (IC) design community into mainstream biocomputing research. Integrating huge number of processing cores on a single chip can help realize orders of magnitude improvement in performance and eventually will bridge the gap between data generation and data processing. In this project our aim is to design NoC-based hardware accelerators for different biocomputing applications, like sequence alignment and phylogenetic tree construction.
• Sustainable Computing: While traditional cluster computers are more constrained by power and cooling costs for solving extreme-scale (or exascale) problems, the continuing progress and integration levels in silicon technologies make possible complete end-user systems on a single chip. This massive level of integration makes modern multicore chips all pervasive in domains ranging from climate forecasting and astronomical data analysis, to consumer electronics, smart phones, and biological applications. Consequently, designing multicore chips for exascale computing while using the embedded systems design principles looks like a promising alternative to traditional cluster-based solutions. This project aims to investigate new, far-reaching design methodologies that can help breaking the energy efficiency wall in massively integrated single-chip computing platforms.
• Machine Learning inspired Three-dimensional (3D) NoC Architectures: Three-dimensional (3D) Network-on-Chip (NoC) is an emerging technology that has the potential to achieve high performance with low power consumption for multicore chips. However, to fully realize their potential, we need to consider novel 3D NoC architectures. In this work, inspired by the inherent advantages of small-world (SW) 2D NoCs, we explore the design space of SW network-based 3D NoC architectures. We leverage machine learning to intelligently explore the design space to optimize the placement of both planar and vertical communication links for energy efficiency.