High Performance Computer Systems Research Group
School of Electrical Engineering and Computer Science -- Washington State University
Publications
2009
M.
Turi and J. G. Delgado-Frias, “Decreasing Energy Consumption in Address
Decoders by Means of Selective Precharge Schemes,” Microelectronics
Journal, 2009
D.
R. Blum and J. G. Delgado-Frias, “Delay and Energy Analysis of SEU and
SET-Tolerant Pipeline Latches and Flip-Flops,” IEEE Transactions on
Nuclear Science, vol. 56, no. 3, pp.
1618-1628,
June 2009.
R.
Guo and J. G. Delgado-Frias, “IP Routing table compaction and sampling
schemes to enhance TCAM cache performance,” Journal of Systems
Architecture, vol. 55, issue 1, pp. 61–69, January 2009.
Z.
Zhang, Y. Liu, J. Nyathi, and J. G. Delgado-Frias, “Performance of CNFET
SRAM Cells under Diameter Variation Corners,”
MWSCAS 2009. 52nd Midwest Symposium on
Circuits and Systems,
pp. 547-550,
Cancun, Mexico, 2-5 Aug. 2009.
K.
Robinson and J. G. Delgado-Frias, “Fault Avoidance in Medium-Grain
Reconfigurable Hardware Architectures,” International Conference on
Engineering of Reconfigurable Systems and Algorithms, Las Vegas,
Nevada, July 13-16, 2009.
2008
M.
Turi and J. G. Delgado-Frias, “High-Performance Low-Power Selective
Precharge Schemes for Address Decoders,” IEEE Transactions on Circuits
and Systems, II, vol. 55, no. 9, pp. 917-921, September 2008.
P.
Sapaty, M.Sugisaka, J. Delgado-Frias, J. Filipe, N. Mirenkov, “Intelligent
management of distributed dynamic sensor networks,”
Artificial Life and
Robotics,
vol. 12, no. 1-2, pp. 81-87, March 2008.
L.
Zhao, J. G. Delgado-Frias, and K. Sivakumar,
“Performance Analysis of Multipath Transmission over 802.11-based Multihop
Ad Hoc Networks: A Cross-Layer Perspective,” IET (formerly IEE)
Communications, vol. 2, no. 2, pp. 380-387, February 2008.
M.
Myjak and J. G. Delgado-Frias, "A Medium-Grain Reconfigurable Architecture
for DSP: VLSI Design, Benchmark Mapping, and Performance,”
IEEE
Transactions on VLSI Systems,
vol. 16, no. 1, pp.
14-23, January 2008.
R.
R. Rydberg, J. Nyathi, and J. G. Delgado-Frias, “Clock
skew tolerant communication scheme for SoC IP blocks,”
MWSCAS 2008.
51st Midwest Symposium on
Circuits and
Systems,
pp. 358 – 361, 10-13 Aug. 2008.
D.
R. Blum and J. G. Delgado-Frias, “Multiple
node upset mitigation in TPDICE-based pipeline memory structures,”
MWSCAS
2008. 51st Midwest Symposium on
Circuits and
Systems,
pp. 314 – 317, Aug. 10-13, 2008.
FPGA
Schemes with Optimized Routing for the Advanced Encryption Standard,”
ERSA’2008 The International Conference on Engineering of
Reconfigurable Systems and Algorithms,
Las Vegas, Nevada,
USA, July 14 - 17, 2008
M.
Turi and J. G. Delgado-Frias, “High-Performance Low-Power AND and
Sense-Amp Address Decoders with Selective Precharging”
IEEE International
Symposium on Circuits and Systems,
Seattle, WA, May 2008.
2007
R.
He and J. G. Delgado-Frias, “Fault Tolerant Interleaved Switching Fabrics
for Scalable High Performance Routers,”
IEEE Transactions
on Parallel and Distributed Systems,
vol. 18, no. 12, pp. 1727-1739, Dec. 2007.
M. Myjak and J. G. Delgado-Frias, “Medium-Grain Cells for Reconfigurable DSP Hardware,” IEEE Transactions on Circuits and Systems, I: Fundamental Theory and Applications, vol. 54, no 6, pp. 1255-1265, June 2007.
M.
Myjak and J. G. Delgado-Frias, “A Two-Level Reconfigurable Cell Array for
Digital Signal Processing,” The Microelectronic Engineering Journal,
vol. 84, no. 2, pp. 244-253, February 2007.
P.
Sapaty, M.Sugisaka, R. Finkelstein, J. Delgado-Frias, N. Mirenkov,
“Emergent societies: advanced IT support of crisis relief missions,”
Artificial Life and Robotics, vol. 11, no. 1, pp. 116-122, January
2007.
S. Medidi,
J. G. Delgado-Frias and H. Liu, “Hardware/Software Solution to Improve
Security in Mobile Ad-hoc Networks,” Mobile and Wireless Network
Security and Privacy, S. Kami Makki, Peter Reiher, Kia Makki, Niki Pissinou
and Shamila Makki (Eds), Springer pp. 205-217, 2007.
L.
Zhao and J. G. Delgado-Frias, “MARS:
Misbehavior Detection in Ad Hoc Networks,”
IEEE GLOBECOM
2007,
Washington, D.C., Nov. 26 – 30, 2007.
R.
He and J. G. Delgado-Frias, “Redundant
Array of Independent Fabrics -An Architecture for Next Generation Network,”
IEEE
GLOBECOM 2007,
Washington, D.C., Nov. 26 – 30, 2007.
H.
Liu, J. G. Delgado-Frias, and S. Medidi, “Using a
Cache Scheme to Detect Misbehaving Nodes in Mobile Ad Hoc Networks,”
15th IEEE International Conference on Networks ICON2007, Adelaide,
Australia,
19-21 Nov. 2007.
M.
Turi and J. G. Delgado-Frias, “Reducing Power in Memory Decoders by Means
of Selective Precharge Schemes,” 50th IEEE Int. Midwest Symposium on
Circuits and Systems, August 5-8, 2007.
H.
Liu, J. G. Delgado-Frias, and S. Medidi, “Using
a Cache Scheme to Detect Selfish Nodes in Mobile Ad Hoc Networks,”
IASTED Int. Conf. on
Communications, Internet, & Information
Technology,
pp. 61-66, July 2-4, 2007.
H.
Liu, J. G. Delgado-Frias, and S. Medidi, “Using
a Two-Timer Scheme to Detect Selfish Nodes in Mobile Ad-hoc Networks,”
IASTED
Int. Conf. on
Communications, Internet, & Information
Technology,
pp. 179-184, July 2-4, 2007.
R.
Guo and J. G. Delgado-Frias, “A
Novel Compaction Scheme for Routing Tables in TCAM to Enhance Cache Hit
Rate,”
IASTED
Int. Conf. on
Communications,
Internet, & Information Technology, pp. 204-209,
July 2
– 4, 2007.
J.
Liu and J. G. Delgado-Frias, “A DAMQ Shared
Buffer Scheme for Network-on-Chip,” IASTED
Int. Conf. on
Circuits, Signals,
and Systems,
pp. 53-58, July 2 – 4, 2007.
R.
Guo, J. G. Delgado-Frias, and S. Wong, “Cache
Replacement Policies for IP Address Lookups,”
IASTED
Int. Conf. on
Circuits, Signals,
and Systems, pp. 70-75,
July 2
– 4, 2007.
D.
R. Blum, J. G. Delgado-Frias, and S. Ray, “SEU
and SET-Tolerant Memory-Based Reconfigurable DSP Processor,”
13th
NASA Symposium on VLSI Design,
June 2007.
D.
R. Blum and J. G. Delgado-Frias, “Hardened by Design Techniques for
Implementing Multiple-Bit Upset Tolerant Static Memories”
2007 IEEE
International Symposium on Circuits and Systems,
pp. 2786-2789, New Orleans, LA, May 27-30, 2007.
2006
D.
R. Blum and J. G. Delgado-Frias, “Schemes for Eliminating Transient-Width
Clock Overhead from SET-Tolerant Memory Based Systems,” IEEE
Transactions on Nuclear Science, vol. 53, no. 3, pp. 1564-1573, June
2006.
S.
B. Tatapudi and J. G. Delgado-Frias, “A Mesochronous Pipelining Scheme for
High- Performance Digital Systems,” IEEE Transactions on Circuits and
Systems, I: Fundamental Theory and Applications, vol. 53, no. 5, pp.
1078-1088, May 2006.
P. Sapaty, M.Sugisaka, R. Finkelstein, J. Delgado-Frias, N. Mirenkov,
“Advanced IT Support of Crisis Relief Missions,” Journal of Emergency Management, Volume 4, Number 4, pp.
29-36, July/August 2006.
R.
He and J. G. Delgado-Frias, “Interleaved Multistage Switching Fabrics for
Scalable High Performance Routers,” IEEE
GLOBECOM 2006, San Francisco, Calif. Nov. 27 – Dec.1, 2006.
M.
J. Myjak, J. G. Delgado-Frias, and S.K. Jeon, “An Energy-Efficient
Differential Flip-Flop for Deeply Pipelined Systems,”
49th IEEE Int.
Midwest Symposium on Circuits and Systems,
August 2006.
S.
B. Tatapudi and J. G. Delgado-Frias, “A Reduced Clock Delay Approach for
High Performance Mesochronous Pipeline,”
49th IEEE Int.
Midwest Symposium on Circuits and Systems,
August 2006.
K.
Blomster and J. G. Delgado-Frias, “High Performance Memory Read Using
Cross-Coupled Pull-up Circuitry,”
49th IEEE Int.
Midwest Symposium on Circuits and Systems,
August 2006.
J.
Liu and J. G. Delgado-Frias, “A Shared Self-Compacting Buffer for
Network-On-Chip Systems,”
49th IEEE Int.
Midwest Symposium on Circuits and Systems,
August 2006.
J.
Nyathi, R. R. Rydberg III, and J. G. Delgado-Frias, “Wave-Pipelining
the Global Interconnect to Reduce the Associated Delays,” 49th
IEEE Int. Midwest Symposium on Circuits and Systems, August 2006.
D.
R. Blum and J. G. Delgado-Frias “SEU and SET-Tolerant Pipelined Systems,”
Second IEEE International Conference on Space Mission Challenges for
Information Technology (SMC-IT 2006), Pasadena, CA, July 17-20, 2006.
(Best student paper award)
L.
Zhao and J. G. Delgado-Frias, “On Throughput of Multipath Data
Transmission over Multihop Ad Hoc Networks,” IASTED International
Conference on Wireless Sensor Networks (WSN 2006), July 3-5, 2006.
L.
Zhao and J. G. Delgado-Frias, “Performance
Analysis of Multipath Data Transmission in Multihop Ad Hoc Networks,”
IEEE International Workshop on Wireless Ad-hoc and Sensor Networks,
New York, June 28-30, 2006.
M.
J. Myjak, J. K. Larson, and J. G. Delgado-Frias, “Mapping and Performance
of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture,”
International Conference on Engineering of Reconfigurable Systems and
Algorithms, Las Vegas, Nevada, June 26-29, 2006.
L.
Zhao and J. G. Delgado-Frias, “Multipath Routing Based Secure Data
Transmission in Ad-Hoc Networks,” IEEE Int. Conf. on Wireless and
Mobile Computing, Networking and Communications (WiMob 2006),
Montreal, Canada
June
19-21, 2006.
M.
J. Myjak, and J. G. Delgado-Frias, “Superpipelined reconfigurable hardware
for DSP,” 2006 IEEE International Symposium on Circuits and Systems,
Kos, Greece, May 21-24, 2006.
S.
B. Tatapudi and J. G. Delgado-Frias, “A Mesochronous Pipeline Scheme for
High Performance Low Power Digital Systems,” 2006 IEEE International
Symposium on Circuits and Systems, Kos, Greece, May 21-24, 2006.
P.
Sapaty, M.Sugisaka, R. Finkelstein, J. Delgado-Frias, N. Mirenkov, “Emergent
Societies: An advanced IT support of crisis relief missions,” 11th
International Symposium on Artificial Life and Robotics,
Oita, Japan, January 23-25, 2006
2005
J.
G. Delgado-Frias, J. Nyathi and S.
Tatapudi, “Decoupled Dynamic
Ternary Content Addressable Memories,” IEEE Trans. on Circuits and Systems, I: Fundamental Theory
and Applications,
vol. 52, no. 10, pp. 2139-2147 Oct. 2005.
D.R.
Blum and J.G. Delgado-Frias, “Comparison of SET-Resistant Approaches for
Memory-Based Architectures,” Proc. of the 12th NASA Symposium on VLSI
Design, Coeur d'Alene, ID, Oct. 2005
K.
Blomster and J. G. Delgado-Frias, “Reducing Power and Delay in Memory
Cells Using Virtual Source Transistors,” 48th IEEE Int. Midwest
Symposium on Circuits and Systems, Aug. 2005.
S.
B. Tatapudi and J. G. Delgado-Frias,
“Designing Pipelined Systems with a Clock Period Approaching
Pipeline Register Delays,” 48th IEEE Int. Midwest Symposium on
Circuits and Systems, Aug. 2005.
M.
J. Myjak, and J. G. Delgado-Frias, “A Bit-Serial Cell for
Reconfigurable DSP Hardware,” 48th IEEE Int. Midwest Symposium on
Circuits and Systems, Aug. 2005.
A.
Widjaja and J. G. Delgado-Frias, “A High-Performance Unicast
Configuration Scheme for an H-Tree Based Reconfigurable Hardware,” 48th
IEEE Int. Midwest Symposium on Circuits and Systems, Aug. 2005.
J.
Levi, J. Nyathi, and J. G. Delgado-Frias, “High Performance Parallel
Addition Using Hybrid Wave-Pipelining,” 48th
IEEE Int. Midwest
Symposium on Circuits and Systems, Aug. 2005.
L.
Y. Yang, H. R. Arabnia, Y. Li, S. N. Salloum, and J. G. Delgado-Frias
(Eds), Proceedings of the 2005 International Conference on Computer
Design, CSREA Press, 2005.
D.
R. Blum, M. J. Myjak, and J. G. Delgado-Frias, “Enhanced
Fault-Tolerant Data Latches for Deep Submicron CMOS,” The 2005
International Conference on Computer Design, pp. 28-34, Las Vegas,
June 2005.
S.
B. Tatapudi and J. G. Delgado-Frias, “A Pipelined Multiplier Using A
Hybrid Wave-Pipelining Scheme,” The 2005
International Conference on Computer Design, pp. 191-197, Las Vegas, June
2005.
M.
J. Myjak, and J. G. Delgado-Frias, “A Symmetric Differential Clock
Generator for Bit-Serial Hardware,” The 2005
International Conference on Computer Design, pp. 159-164, Las Vegas, June 2005.
J.
Liu and J. G. Delgado-Frias, “DAMQ Self-Compacting Buffer Schemes
for Systems with Network-On-Chip,” The 2005 International
Conference on Computer Design, pp. 97-103, Las Vegas, June
2005.
R.
R. Rydberg III, J. Nyathi, and J. G. Delgado-Frias, “A
Distributed FIFO Scheme for on Chip Communication,” IEEE
Int.
Symp. on Circuits and Systems (ISCAS 2005), Japan, May 2005.
S.
B. Tatapudi and J. G. Delgado-Frias, “A High Performance Hybrid Wave
Pipelined Multiplier,” IEEE Computer Society Annual Symp. on VLSI,
pp. 282-283, May 11-12, 2005.
More publications (2001 to 2004).
