Book Chapter

B1. "Impact of TSV and Device Scaling on the Quality of 3D ICs," in More than Moore Technologies for Next Generation Computer Design
edited by Rasit Topaloglu, Springer, 2015 (ISBN 978-1-4939-2163-8).
Dae Hyun Kim and Sung Kyu Lim




Journal

2018
J16. [IEEE TCAD] Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits
   Inki Hong and Dae Hyun Kim
   Vol. 37, No. 4, Apr. 2018, pp. 845-854.

J15. [IEEE TCAD] Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs
   Sheng-En David Lin and Dae Hyun Kim
   Vol. 37, No. 4, Apr. 2018, pp. 845-854.

2016
J14. [IEEE D&T] Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2
   Dae Hyun Kim and Sung Kyu Lim
   Vol. 33, No. 2, Apr. 2016, pp. 7-8.

2015
J13. [IEEE D&T] Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities
   Dae Hyun Kim and Sung Kyu Lim
   Vol. 32, No. 4, Aug. 2015, pp. 8-22.

J12. [IEEE D&T] Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools
   Dae Hyun Kim and Sung Kyu Lim
   Vol. 32, No. 4, Aug. 2015, pp. 6-7.

J11. [IEEE TC] Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)
   Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
   Vol. 64, No. 1, Jan. 2015, pp. 112-125.

2014
J10. [Microelectronics Journal] Simulation of System Backend Dielectric Reliability
   Chang-Chih Chen, Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
   Vol. 45, No. 10, Oct. 2014, pp. 1327-1334.

J9. [IEEE TCAD] TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs
   Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
   Vol. 33, No. 9, Sep. 2014, pp. 1384-1395.

J8. [IEEE TVLSI] Backend Dielectric Reliability Full Chip Simulator
   Muhammad Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
   Vol. 22, No. 8, Aug. 2014, pp. 1750-1762.

2013
J7. [IEEE TVLSI] Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
   Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim
   Vol. 21, No. 5, May 2013, pp. 862-874.

2012
J6. [Microelectronics Reliability] Backend dielectric reliability simulator for microprocessor system
   Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
   Vol. 52, No. 9-10, Sep. 2012, pp. 1953-1959.

J5. [IEEE JETCAS] Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices
   Dae Hyun Kim and Sung Kyu Lim
   Vol. 2, No. 2, June 2012, pp. 240-248.

2011
J4. [IEEE TCPMT] Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System
   Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay
   Vol. 1, No. 11, Nov. 2011, pp. 1718-1727.

J3. [Microelectronics Reliability] Impact of irregular geometries on low-k dielectric breakdown
   Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
   Vol. 51, No. 9-11, Sep. 2011, pp. 1582-1586.

J2. [IEEE TCPMT] Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling
   Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
   Vol. 1, No. 2, Feb. 2011, pp. 168-180.

2010
J1. [Microelectronics Reliability] Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown
   Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
   Vol. 50, No. 9-11, Sep. 2010, pp. 1341-1346.




Conference

2018
C28. [ISPD] Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid
   Sheng-En David Lin and Dae Hyun Kim
   Mar. 2018, pp. 18-25.

2017
C27. [ISQED] A Legalization Algorithm for Multi-Tier Gate-Level Monolithic Three-Dimensional Integrated Circuits
   Yiting Chen and Dae Hyun Kim
   Mar. 2017, pp. 277-282.

2016
C26. [ISQED] Optimization of Dynamic Power Consumption in Multi-Tier Gate-Level Monolithic 3D ICs
   Sheng-En David Lin, Partha Pratim Pande, and Dae Hyun Kim
   Mar. 2016, pp. 29-34.

2015
C25. [ICCAD] Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach
   Sourav Das, Janardhan Rao Doppa, Dae Hyun Kim, Partha Pande, and Krishnendu Chakrabarty
   Nov. 2015, pp. 705-712.

C24. [GLSVLSI] Small-World Network Enabled Energy Efficient and Robust 3D NoC Architecture
   Sourav Das, Dongjin Lee, Dae Hyun Kim, and Partha Pratim Pande
   May 2015, pp. 133-138.

2013
C23. [ASPDAC] Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs
   Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
   Jan. 2013, pp. 687-692.

2012
C22. [ESREF] Backend Dielectric Reliability Simulator for Microprocessor System
   Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
   Oct. 2012.

C21. [SRC Techcon] Design Quality Trade-off Studies for 3D ICs Built with Sub-Micron TSVs and Future Devices
   Dae Hyun Kim and Sung Kyu Lim
   Sep. 2012.

C20. [IRPS] Backend Dielectric Chip Reliability Simulator for Complex Interconnect Geometries
   Chang-Chih Chen, Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
   Apr. 2012, pp. BD.4.1-BD.4.8.

C19. [ISQED] Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
   Kaiyuan Yang, Dae Hyun Kim, and Sung Kyu Lim
   Mar. 2012, pp. 741-747.

C18. [ISSCC] 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
   Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Jounhgo Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
   Feb. 2012, pp. 188-190.

C17. [ASPDAC] Block-level 3D IC Design with Through-Silicon-Via Planning
   Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim
   Jan. 2012, pp. 335-340.

2011
C16. [ISOCC] TSV Density-driven Global Placement for 3D Stacked ICs (invited)
   Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim
   Nov. 2011, pp. 135-138.

C15. [SRC Techcon] A Study on the Impact of Nano-Scale TSVs on 3D IC Designs
   Dae Hyun Kim and Sung Kyu Lim
   Sep. 2011.

C14. [SLIP] Impact of Nano-scale Through-Silicon Vias on the Quality of Today and Future 3D IC Designs
   Dae Hyun Kim, Suyoun Kim, and Sung Kyu Lim
   June 2011, pp. 1-8.

C13. [IITC] Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs
   Dae Hyun Kim and Sung Kyu Lim
   May 2011, pp. 1-3.

C12. [IRPS] Backend Low-k TDDB Chip Reliability Simulator
   Muhammad Bashir, Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim, and Linda Milor
   Apr. 2011, pp. 2C.2.1-2C.2.10.

C11. [ISQED] Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs
   Taigon Song, Chang Liu, Dae Hyun Kim, Jonghyun Cho, Joohee Kim, Jun So Pak, Seungoung Ahn, Joungho Kim, Kihyun Yoon, and Sung Kyu Lim
   Mar. 2011, pp. 122-128.

2010
C10. [ICCAD] Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System
   Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay
   Nov. 2010, 694-697.

C9. [IIRW] TDDB Chip Reliability in Copper Interconnects
   Muhammad Bashir, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
   Oct. 2010, pp. 121-124.

C8. [CICC] Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory
   Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
   Sep. 2010, pp. 1-4.

C7. [DFMY] Enabling 3D Integration Through Optimal Topography
   Dae Hyun Kim, Yen-Kuan Wu, Rasit Onur Topaloglu, and Sung Kyu Lim
   June 2010, pp. 70-73.

C6. [SLIP] Through-Silicon-Via-aware Delay and Power Prediction Model for Buffered Interconnects in 3D ICs
   Dae Hyun Kim and Sung Kyu Lim
   June 2010, pp. 25-31.

2009
C5. [ICCAD] A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout
   Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim
   Nov. 2009, pp. 674-680.

C4. [SLIP] Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs
   Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
   July 2009, pp. 85-92.

C3. [IITC] TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs
   Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
   June 2009, pp. 26-28.

2008
C2. [ICCD] Global Bus Route Optimization with Application to Microarchitectural Design Exploration
   Dae Hyun Kim and Sung Kyu Lim
   Oct. 2008, pp. 658-663.

C1. [ASPDAC] Bus-Aware Microarchitectural Floorplanning
   Dae Hyun Kim and Sung Kyu Lim
   Jan. 2008, pp. 204-208.