Book Chapter
B1. "Impact of TSV and Device Scaling on the Quality of 3D ICs," in More than Moore Technologies for Next Generation Computer Design
edited by Rasit Topaloglu, Springer, 2015 (ISBN 978-1-4939-2163-8).
Dae Hyun Kim and Sung Kyu Lim
Journal
2023
J24. [ACM TODAES] Construction of All Multilayer Monolithic RSMTs and Its Application to Monolithic 3D IC Routing
Monzurul Islam Dewan, Sheng-En David Lin, and Dae Hyun Kim
Vol. 29, No. 1, pp. 17:1-17:28, Dec. 2023.
2022
J23. [ACM TODAES] Design Automation Algorithms for the NP-Separate VLSI Design Methodology
Monzurul Islam Dewan and Dae Hyun Kim
Vol. 27, No. 5, pp. 53:1-53:20, Sep. 2022.
2021
J22. [ACM TODAES] HeM3D: Heterogeneous Manycore Architecture Based on Monolithic 3D Vertical Integration
Aqeeb Iqbal Arka, Biresh Kumar Joardar, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, and Partha Pratim Pande
Vol. 26, No. 2, pp. 16:1-16:21, Mar. 2021.
2020
J21. [IEEE TCAD] NP-Separate: A New VLSI Design Methodology for Area, Power, and Performance Optimization
Monzurul Islam Dewan and Dae Hyun Kim
Vol. 39, No. 12, pp. 5111-5122, Dec. 2020.
J20. [IEEE TCAD] Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid and Its Applications to VLSI Design
Sheng-En David Lin and Dae Hyun Kim
Vol. 39, No. 6, pp. 1165-1176, June 2020.
J19. [IEEE TVLSI] Inter-Tier Process-Variation-Aware Monolithic 3-D NoC Design Space Exploration
Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, and Partha Pratim Pande
Vol. 28, No. 3, pp. 686-699, Mar. 2020.
2019
J18. [IEEE TETC] Wire Length Characteristics of Multi-Tier Gate-Level Monolithic 3D ICs
Sheng-En David Lin and Dae Hyun Kim
Vol. 7, No. 2, pp. 301-310, Apr-Jun 2019.
2018
J17. [ACM JETC] Design Space Exploration of 3D Network-on-Chip: A Sensitivity-based Optimization Approach
Dongjin Lee, Sourav Das, Dae Hyun Kim, Janardhan Rao Doppa, and Partha Pratim Pande
Vol. 14, No. 3, pp. 32:1-32:26, Oct. 2018.
J16. [IEEE TCAD] Analysis of Performance Benefits of Multitier Gate-Level Monolithic 3-D Integrated Circuits
Inki Hong and Dae Hyun Kim
Vol. 37, No. 8, pp. 1614-1626, Aug. 2018.
J15. [IEEE TCAD] Detailed-Placement-Enabled Dynamic Power Optimization of Multitier Gate-Level Monolithic 3-D ICs
Sheng-En David Lin and Dae Hyun Kim
Vol. 37, No. 4, pp. 845-854, Apr. 2018.
2016
J14. [IEEE D&T] Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools - Part 2
Dae Hyun Kim and Sung Kyu Lim
Vol. 33, No. 2, pp. 7-8, Apr. 2016.
2015
J13. [IEEE D&T] Physical Design and CAD Tools for 3-D Integrated Circuits: Challenges and Opportunities
Dae Hyun Kim and Sung Kyu Lim
Vol. 32, No. 4, pp. 8-22, Aug. 2015.
J12. [IEEE D&T] Guest Editors' Introduction: Advances in 3-D Integrated Circuits, Systems, and CAD Tools
Dae Hyun Kim and Sung Kyu Lim
Vol. 32, No. 4, pp. 6-7, Aug. 2015.
J11. [IEEE TC] Design and Analysis of 3D-MAPS (3D Massively Parallel Processor with Stacked Memory)
Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
Vol. 64, No. 1, pp. 112-125, Jan. 2015.
2014
J10. [Microelectronics Journal] Simulation of System Backend Dielectric Reliability
Chang-Chih Chen, Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
Vol. 45, No. 10, pp. 1327-1334, Oct. 2014.
J9. [IEEE TCAD] TSV-Aware Interconnect Distribution Models for Prediction of Delay and Power Consumption of 3-D Stacked ICs
Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
Vol. 33, No. 9, pp. 1384-1395, Sep. 2014.
J8. [IEEE TVLSI] Backend Dielectric Reliability Full Chip Simulator
Muhammad Bashir, Chang-Chih Chen, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
Vol. 22, No. 8, pp. 1750-1762, Aug. 2014.
2013
J7. [IEEE TVLSI] Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout
Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim
Vol. 21, No. 5, pp. 862-874, May 2013.
2012
J6. [Microelectronics Reliability] Backend dielectric reliability simulator for microprocessor system
Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
Vol. 52, No. 9-10, pp. 1953-1959, Sep. 2012.
J5. [IEEE JETCAS] Design Quality Trade-Off Studies for 3-D ICs Built With Sub-Micron TSVs and Future Devices
Dae Hyun Kim and Sung Kyu Lim
Vol. 2, No. 2, pp. 240-248, June 2012.
2011
J4. [IEEE TCPMT] Pre-Bond and Post-Bond Test and Signal Recovery Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3-D System
Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay
Vol. 1, No. 11, pp. 1718-1727, Nov. 2011.
J3. [Microelectronics Reliability] Impact of irregular geometries on low-k dielectric breakdown
Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
Vol. 51, No. 9-11, pp. 1582-1586, Sep. 2011.
J2. [IEEE TCPMT] Fast and Accurate Analytical Modeling of Through-Silicon-Via Capacitive Coupling
Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
Vol. 1, No. 2, pp. 168-180, Feb. 2011.
2010
J1. [Microelectronics Reliability] Methodology to determine the impact of linewidth variation on chip scale copper/low-k backend dielectric breakdown
Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
Vol. 50, No. 9-11, pp. 1341-1346, Sep. 2010.
Conference
2023
C37. [ARITH] Dual-Purpose Hardware Algorithms and Architectures - Part 2: Integer Division
Jihee Seo and Dae Hyun Kim
pp. 1-8, Sep. 2023.
C36. [ARITH] Dual-Purpose Hardware Algorithms and Architectures - Part 1: Floating-Point Division
Jihee Seo and Dae Hyun Kim
pp. 24-31, Sep. 2023.
2022
C35. [AAAI] Bayesian Optimization over Permutation Spaces
Aryan Deshwal, Syrine Belakaria, Janardhan Rao Doppa, and Dae Hyun Kim
pp. 6515-6523, Feb. 2022.
2020
C34. [DATE] Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore Chips
Shouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae Hyun Kim, Janardhan Rao Doppa, and Partha Pratim Pande
pp. 1752-1757, Mar. 2020.
2019
C33. [ARITH] High-Throughput Multiplier Architectures Enabled by Intra-Unit Fast Forwarding
Jihee Seo and Dae Hyun Kim
pp. 143-150, June 2019.
C32. [ISPD] Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing
Sheng-En David Lin and Dae Hyun Kim
pp. 57-64, Apr. 2019.
C31. [DATE] Dependency-Resolving Intra-Unit Pipeline Architecture for High-Throughput Multipliers
Jihee Seo and Dae Hyun Kim
pp. 918-921, Mar. 2019.
C30. [ISQED] Routing Complexity Minimization of Monolithic Three-Dimensional Integrated Circuits
Sheng-En David Lin and Dae Hyun Kim
pp. 329-334, Mar. 2019.
C29. [ISQED] A Non-Slicing 3-D Floorplan Representation for Monolithic 3-D IC Design
Shantonu Das and Dae Hyun Kim
pp. 323-328, Mar. 2019.
2018
C28. [ISPD] Construction of All Rectilinear Steiner Minimum Trees on the Hanan Grid
Sheng-En David Lin and Dae Hyun Kim
pp. 18-25, Mar. 2018.
2017
C27. [ISQED] A Legalization Algorithm for Multi-Tier Gate-Level Monolithic Three-Dimensional Integrated Circuits
Yiting Chen and Dae Hyun Kim
pp. 277-282, Mar. 2017.
2016
C26. [ISQED] Optimization of Dynamic Power Consumption in Multi-Tier Gate-Level Monolithic 3D ICs
Sheng-En David Lin, Partha Pratim Pande, and Dae Hyun Kim
pp. 29-34, Mar. 2016.
2015
C25. [ICCAD] Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning Approach
Sourav Das, Janardhan Rao Doppa, Dae Hyun Kim, Partha Pande, and Krishnendu Chakrabarty
pp. 705-712, Nov. 2015.
C24. [GLSVLSI] Small-World Network Enabled Energy Efficient and Robust 3D NoC Architecture
Sourav Das, Dongjin Lee, Dae Hyun Kim, and Partha Pratim Pande
pp. 133-138, May 2015.
2013
C23. [ASPDAC] Block-level Designs of Die-to-Wafer Bonded 3D ICs and Their Design Quality Tradeoffs
Krit Athikulwongse, Dae Hyun Kim, Moongon Jung, and Sung Kyu Lim
pp. 687-692, Jan. 2013.
2012
C22. [ESREF] Backend Dielectric Reliability Simulator for Microprocessor System
Chang-Chih Chen, Fahad Ahmed, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
Oct. 2012.
C21. [SRC Techcon] Design Quality Trade-off Studies for 3D ICs Built with Sub-Micron TSVs and Future Devices
Dae Hyun Kim and Sung Kyu Lim
Sep. 2012.
C20. [IRPS] Backend Dielectric Chip Reliability Simulator for Complex Interconnect Geometries
Chang-Chih Chen, Muhammad Bashir, Linda Milor, Dae Hyun Kim, and Sung Kyu Lim
pp. BD.4.1-BD.4.8, Apr. 2012.
C19. [ISQED] Design Quality Tradeoff Studies for 3D ICs Built with Nano-scale TSVs and Devices
Kaiyuan Yang, Dae Hyun Kim, and Sung Kyu Lim
pp. 741-747, Mar. 2012.
C18. [ISSCC] 3D-MAPS: 3D Massively Parallel Processor with Stacked Memory
Dae Hyun Kim, Krit Athikulwongse, Michael B. Healy, Mohammad M. Hossain, Moongon Jung, Ilya Khorosh, Gokul Kumar, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Shreepad Panth, Mohit Pathak, Minzhen Ren, Guanhao Shen, Taigon Song, Dong Hyuk Woo, Xin Zhao, Joungho Kim, Ho Choi, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
pp. 188-190, Feb. 2012.
C17. [ASPDAC] Block-level 3D IC Design with Through-Silicon-Via Planning
Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim
pp. 335-340, Jan. 2012.
2011
C16. [ISOCC] TSV Density-driven Global Placement for 3D Stacked ICs (invited)
Dae Hyun Kim, Rasit Onur Topaloglu, and Sung Kyu Lim
pp. 135-138, Nov. 2011.
C15. [SRC Techcon] A Study on the Impact of Nano-Scale TSVs on 3D IC Designs
Dae Hyun Kim and Sung Kyu Lim
Sep. 2011.
C14. [SLIP] Impact of Nano-scale Through-Silicon Vias on the Quality of Today and Future 3D IC Designs
Dae Hyun Kim, Suyoun Kim, and Sung Kyu Lim
pp. 1-8, June 2011.
C13. [IITC] Impact of Through-Silicon-Via Scaling on the Wirelength Distribution of Current and Future 3D ICs
Dae Hyun Kim and Sung Kyu Lim
pp. 1-3, May 2011.
C12. [IRPS] Backend Low-k TDDB Chip Reliability Simulator
Muhammad Bashir, Dae Hyun Kim, Krit Athikulwongse, Sung Kyu Lim, and Linda Milor
pp. 2C.2.1-2C.2.10, Apr. 2011.
C11. [ISQED] Analysis of TSV-to-TSV Coupling with High-Impedance Termination in 3D ICs
Taigon Song, Chang Liu, Dae Hyun Kim, Jonghyun Cho, Joohee Kim, Jun So Pak, Seungoung Ahn, Joungho Kim, Kihyun Yoon, and Sung Kyu Lim
pp. 122-128, Mar. 2011.
2010
C10. [ICCAD] Design Method and Test Structure to Characterize and Repair TSV Defect Induced Signal Degradation in 3D System
Minki Cho, Chang Liu, Dae Hyun Kim, Sung Kyu Lim, and Saibal Mukhopadhyay
694-697, Nov. 2010.
C9. [IIRW] TDDB Chip Reliability in Copper Interconnects
Muhammad Bashir, Dae Hyun Kim, Sung Kyu Lim, and Linda Milor
pp. 121-124, Oct. 2010.
C8. [CICC] Design and Analysis of 3D-MAPS: A Many-Core 3D Processor with Stacked Memory
Michael B. Healy, Krit Athikulwongse, Rohan Goel, Mohammad M. Hossain, Dae Hyun Kim, Young-Joon Lee, Dean L. Lewis, Tzu-Wei Lin, Chang Liu, Moongon Jung, Brian Ouellette, Mohit Pathak, Hemant Sane, Guanhao Shen, Dong Hyuk Woo, Xin Zhao, Gabriel H. Loh, Hsien-Hsin S. Lee, and Sung Kyu Lim
pp. 1-4, Sep. 2010.
C7. [DFMY] Enabling 3D Integration Through Optimal Topography
Dae Hyun Kim, Yen-Kuan Wu, Rasit Onur Topaloglu, and Sung Kyu Lim
pp. 70-73, June 2010.
C6. [SLIP] Through-Silicon-Via-aware Delay and Power Prediction Model for Buffered Interconnects in 3D ICs
Dae Hyun Kim and Sung Kyu Lim
pp. 25-31, June 2010.
2009
C5. [ICCAD] A Study of Through-Silicon-Via Impact on the 3D Stacked IC Layout
Dae Hyun Kim, Krit Athikulwongse, and Sung Kyu Lim
pp. 674-680, Nov. 2009.
C4. [SLIP] Through-Silicon-Via Aware Interconnect Prediction and Optimization for 3D Stacked ICs
Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
pp. 85-92, July 2009.
C3. [IITC] TSV-aware Interconnect Length and Power Prediction for 3D Stacked ICs
Dae Hyun Kim, Saibal Mukhopadhyay, and Sung Kyu Lim
pp. 26-28, June 2009.
2008
C2. [ICCD] Global Bus Route Optimization with Application to Microarchitectural Design Exploration
Dae Hyun Kim and Sung Kyu Lim
pp. 658-663, Oct. 2008.
C1. [ASPDAC] Bus-Aware Microarchitectural Floorplanning
Dae Hyun Kim and Sung Kyu Lim
pp. 204-208, Jan. 2008.